1. Field
Example embodiments are directed to a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the same, and for example, to a dual metal gate CMOS semiconductor device and a method of fabricating the same.
2. Description of the Related Art
To satisfy demand for higher integration and faster operation speeds of CMOS semiconductor devices, gate insulating layers and gate electrodes may be made thin. High-k gate insulating layers having higher dielectric constants than SiO2 may be developed so as to improve upon the physical characteristics and/or manufacturing processes caused by thinning the SiO2 insulating layers. A high-k gate insulating material may be used to thicken an insulating layer to a thickness greater than an effective oxide thickness, and may reduce a leakage current of the insulating layer. It may be difficult to use a high-k material as a gate insulating layer due to a number of considerations, for example compatibility problems with polycrystalline silicon (poly-Si), lack of understanding of a fixed charge, interface control difficulty, lowering of mobility, a higher gate depletion layer, and many others.
In a MOS transistor having a metal inserted poly-Si stack (MIPS) structure as seen in the related art, a depletion layer may not be formed in a gate, and dopant may not penetrate into an insulating layer. It may be difficult to modulate a work function due to implantation of dopant caused by an inserted metal. Thus, in examples of CMOS semiconductor device, gate structures or gate materials having different work functions may be used for nMOS and pMOS transistors.
Related art also discloses a dual metal gate using a metal that may have an n+ function for an nMOS area and a metal that may have a p+ work function for a pMOS area.
Related art also suggests a method of forming a dual metal gate using a method of that may additionally insert a metal layer into an nMOS or pMOS area.